1. Field of the Invention
The invention relates to methods for evaluating timing in integrated circuits and more particularly to methods and systems for evaluating timing of signals.
2. Background Description
In circuit design, one signal may need to arrive at a particular point in a circuit path before another signal. For example, a signal representing a stable data value may need to arrive at a memory element (e.g., a flip-flop or latch) before the clock signal that stores the value in the memory element. Alternatively, a signal representing a change in a data value may need to arrive at a memory element after the clock signal that stored the last data value. Two paths along which signals propagate so as to arrive at a particular pair of points (e.g., clock and data pins of a flip-flop) in a defined relationship with one another, as in the examples above, are often referred to as racing paths. Each set of racing paths typically includes an early path and a late path. The comparison of a pair of early and late mode signals to determine whether a particular requirement on their relative arrival times is met is called a timing test. An early mode signal or arrival time is the earliest time at which the value on a net or at a point can change from its previous cycle stable value, and a late mode signal or arrival time is the latest time at which the value on a net or at a point can settle to its final stable value for the current cycle.
Static timing analysis (STA) is a tool used for verification of circuit design and analysis of circuit performance. STA uses delay models to evaluate the delay in circuit paths. Most delay models used for STA can be made to employ parameter distributions, for example, one parameter being gate length, to define best and worst possible integrated circuit performance. The delay models are offered for all process extremes, so the timer can bound delay variations caused by process variations during integrated circuit manufacture, as well as other factors. These process variations can include variations among different integrated circuits, as well as local variations within the same integrated circuit.
In traditional methods of designing application specific integrated circuits (ASICs) and other integrated circuits, the design engineer considers the best-case and worst-case scenarios, for example, by considering and analyzing values for each parameter that are three standard deviations above the mean expected value and three standard deviations below the mean expected value. In other words, both a “fast chip” and a “slow chip” timing analysis are performed. Some manufacturers also use the method of linear combination of delays (LCD) to combine the fast and slow performances to account for variation across the integrated circuit or chip. The LCD method applies different delays to different racing paths, creating an off-tracking margin expressed as a percentage of the delay variation. The off-tracking margin provided by the LCD method is used to account for across-chip variation.
However, since there are a great number of parameters involved in an integrated circuit's timing, the “fast,” “slow,” and LCD methods described above may not account sufficiently for all of the possible variation, since use of LCD parameters sufficient to account for all possible delay variation due to all possible across-chip variation of all parameters on which delays depend would be excessively pessimistic, and LCD parameters are therefore typically chosen to account for most but not all of the possible delay variation which could occur when all or most of the parameters are at their extreme values. Two racing paths that include different cells or elements and different wires will show different sensitivities to global manufacturing process variations, which means that considering all of the parameters at their fastest and all of the parameters at their slowest may be unrealistic. In a comprehensive timing analysis, a design engineer might consider every possible assignment of parameter values to elements in the racing paths. However, such an analysis might be time consuming and impractical.